Материал: mrf1507rev1

Figure 16. Pout versus Pin

4

VDS = 10 V

3

1

0

Figure 17. Drain Current versus Gate Voltage (Typical Device Shown)

C, CAPACITANCE (pF)

Safe Operating Area

VDD = 7.5 V, IDQ = 150 mA, Pout = 8 W

f = 135 MHz

175

VDD = 7.5 V, IDQ = 800 mA, Pout = 8 W

Zin = Conjugate of source impedance with parallel 20 Ω resistor and 82 pF capacitor in series with gate.

ZOL* = Conjugate of the load impedance at given output power, voltage, frequency, and ηD > 50 %.

DESIGN CONSIDERATIONS

The MRF1507 is a common±source, RF power, N±Channel enhancement mode, Lateral Metal±Oxide Semiconductor Field±Effect Transistor (MOSFET). Motorola Application Note AN211A, ªFETs in Theory and Practiceº, is suggested reading for those not familiar with the construction and characteristics of FETs.

This surface mount packaged device was designed primarily for VHF and UHF portable power amplifier applications. Manufacturability is improved by utilizing the tape and reel capability for fully automated pick and placement of parts. However, care should be taken in the design process to insure proper heat sinking of the device.

The major advantages of Lateral RF power MOSFETs include high gain, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage.

MOSFET CAPACITANCES

The physical structure of a MOSFET results in capacitors between all three terminals. The metal oxide gate structure determines the capacitors from gate±to±drain (Cgd), and gate±to±source (Cgs). The PN junction formed during fabrication of the RF MOSFET results in a junction capacitance from drain±to±source (Cds). These capacitances are characterized

as input (Ciss), output (Coss) and reverse transfer (Crss) capacitances on data sheets. The relationships between the

inter±terminal capacitances and those given on data sheets are shown below. The Ciss can be specified in two ways:

1.Drain shorted to source and positive voltage at the gate.

2.Positive voltage of the drain in respect to source and zero volts at the gate.

In the latter case, the numbers are lower. However, neither method represents the actual operating conditions in RF applications.

DRAIN CHARACTERISTICS

One critical figure of merit for a FET is its static resistance in the full±on condition. This on±resistance, RDS(on), occurs in

the linear region of the output characteristic and is specified at a specific gate±source voltage and drain current. The drain±source voltage under these conditions is termed

VDS(on). For MOSFETs, VDS(on) has a positive temperature coefficient at high temperatures because it contributes to the

power dissipation within the device.

BVDSS values for this device are higher than normally required for typical applications. Measurement of BVDSS is not recommended and may result in possible damage to the device.

GATE CHARACTERISTICS

The gate of the RF MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The DC input resistance is very high ± on the order of 109 Ω Ð resulting in a leakage current of a few nanoamperes.

Gate control is achieved by applying a positive voltage to the gate greater than the gate±to±source threshold voltage,

VGS(th).

Gate Voltage Rating Ð Never exceed the gate voltage rating. Exceeding the rated VGS can result in permanent damage to the oxide layer in the gate region.

Gate Termination Ð The gates of these devices are essentially capacitors. Circuits that leave the gate open±circuited or floating should be avoided. These conditions can result in turn±on of the devices due to voltage build±up on the input capacitor due to leakage currents or pickup.

Gate Protection Ð These devices do not have an internal monolithic zener diode from gate±to±source. If gate protection is required, an external zener diode is recommended. Using a resistor to keep the gate±to±source impedance low also helps dampen transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate±drain capacitance. If the gate±to±source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate±threshold voltage and turn the device on.

DC BIAS

Since the MRF1507 is an enhancement mode FET, drain current flows only when the gate is at a higher potential than the source. RF power FETs operate optimally with a quiescent drain current (IDQ), whose value is application dependent. The MRF1507 was characterized at IDQ = 150 mA, which is the suggested value of bias current for typical applications. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters.

The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may require a more elaborate bias system.

GAIN CONTROL

Power output of the MRF1507 may be controlled to some degree with a low power dc control signal applied to the gate, thus facilitating applications such as manual gain control, ALC/AGC and modulation systems. This characteristic is very dependent on frequency and load line.

MOUNTING

The specified maximum thermal resistance of 2°C/W assumes a majority of the 0.065″ x 0.180″ source contact on the back side of the package is in good contact with an appropriate heat sink. As with all RF power devices, the goal

of the thermal design should be to minimize the temperature at the back side of the package.

AMPLIFIER DESIGN

Impedance matching networks similar to those used with bipolar transistors are suitable for the MRF1507. For examples see Motorola Application Note AN721, ªImpedance Matching Networks Applied to RF Power Transistors.º Large± signal impedances are provided, and will yield a good first pass approximation.

Since RF power MOSFETs are triode devices, they are not unilateral. This coupled with the very high gain of the MRF1507 yields a device capable of self oscillation. Stability may be achieved by techniques such as drain loading, input shunt resistive loading, or output to input feedback. The RF test fixture implements a parallel resistor and capacitor in series with the gate, and has a load line selected for a higher efficiency, lower gain, and more stable operating region.

Two±port stability analysis with the MRF1507 S±parameters provides a useful tool for selection of loading or feedback circuitry to assure stable operation. See Motorola Application Note AN215A, ªRF Small±Signal Design Using Two±Port Parametersº for a discussion of two port network theory and stability.