Материал: 74HC158A

Advance Information

Quad 2-Input Data

Selector/Multiplexer

High±Performance Silicon±Gate CMOS

The MC74HC158A is identical in pinout to the LS158. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These devices route 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in inverted form for the HC158A. A high level on the Output Enable input sets all four Y outputs to a high level for the HC158A.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2 to 6V

•Low Input Current: 1μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements

•Chip Complexity: 74 FETs or 18.5 Equivalent Gates

LOGIC DIAGRAM

Pinout: 16±Lead Plastic Package (Top View)

MC74HC158A

ORDERING INFORMATION

MC74HCXXXAN Plastic

MC74HCXXXAD SOIC

MC74HCXXXADT TSSOP

FUNCTION TABLE

X = Don't Care

A0±A3, B0±B3 = the levels of the respective Data±Word inputs.

MAXIMUM RATINGS*

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

tr

90%

10%

tPHL

90%

50%

Output Y

10%

tTHL

Figure 1.

tr

90%

Output Enable

50%

10%

tPLH

90%

50%

Output Y

10%

tTLH

Figure 3.

tf

VCC

GND

tPLH

tTLH

tf

VCC

GND

tPHL

tTHL

Figure 2. Y versus Select, Inverted

*Includes all probe and jig capacitance

Figure 4. Test Circuit

INPUTS

A0±A3 (Pins 2,5,11,14)

Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the HC158A.

B0±B3 (Pins 3,6,10,13)

Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the HC158A.

OUTPUTS

Y0±Y3 (Pins 4,7,9,12)

Data outputs. The selected input nibble is presented at these outputs when the Output Enable input is at a low level.

The data present on these pins is in its inverted form for the HC158A. For the Output Enable input at a high level, the outputs are at a high level for the HC158A.

CONTROL INPUTS

Select (Pin 1)

Nibble select. This input determines the data word to be transferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs.

Output Enable (Pin 15)

Output Enable input. A low level on thisinput allows the selected data to be presented at the outputs. A high level on this input sets all of the outputs to a high level for the HC158A.