Материал: HFA3127_
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HFA3127 |
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S E M I C O N D U C T O R |
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DESIGN INFORMATION
February 1995
Ultra High Frequency Transistor Array
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design information only. No guarantee is implied.
Electrical Specifications at T |
= +25oC |
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A |
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PARAMETERS |
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TEST CONDITIONS |
TYP |
UNITS |
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Noise Figure |
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f = 1.0GHz, VCE = 5V, IC = 5mA, ZS = 50Ω |
3.5 |
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fT Current Gain-Bandwidth Product |
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IC = 1mA, VCE = 5V |
5.5 |
GHz |
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IC = 10mA, VCE = 5V |
8 |
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Power Gain-Bandwidth Product, fMAX |
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IC = 10mA, VCE = 5V |
2.5 |
GHz |
Collector-to-Collector Leakage |
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1 |
pA |
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Collector-to-Base Capacitance |
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0V, 1MHz |
1.6 |
pF |
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Base-to-Emitter Capacitance |
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0V, 1MHz |
2.2 |
pF |
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Collector-to-Emitter Capacitance |
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0V, 1MHz |
1.9 |
pF |
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NOTE: Package interlead capacitance is taken into account for all capacitance measurements.
Typical Performance Curves
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25 |
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IB = 200μA |
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(mA) |
20 |
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IB = 160μA |
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CURRENT |
15 |
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IB =120μA |
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COLLECTOR |
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5 |
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IB = 80μA |
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10 |
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IB = 40μA |
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0 |
2 |
3 |
4 |
5 |
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1 |
COLLECTOR TO EMITTER VOLTAGE (V)
FIGURE 1. NPN COLLECTOR CURRENT vs COLLECTOR TO EMITTER VOLTAGE
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VCE = 3V |
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GAIN |
160 |
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140 |
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CURRENT |
80 |
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120 |
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DC |
100 |
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60 |
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40 |
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20 |
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0 |
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1μ |
10μ |
100μ |
1m |
10m |
100m |
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COLLECTOR CURRENT (A)
FIGURE 3. NPN DC CURRENT GAIN vs COLLECTOR CURRENT
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100m |
VCE = 3V |
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COLLECTORCURRENT BASEANDCURRENT (A) |
10m |
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IC |
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100n |
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IB |
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1m |
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100μ |
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10μ |
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1μ |
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10n |
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1n |
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0.5 |
0.6 |
0.7 |
0.8 |
0.9 |
1.0 |
BASE TO EMITTER VOLTAGE (V)
FIGURE 2. NPN COLLECTOR AND BASE CURRENTS vs BASE TO EMITTER VOLTAGE
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10.0 |
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(GHz) |
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VCE = 3V |
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8.0 |
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PRODUCT |
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VCE = 5V |
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6.0 |
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VCE = 1V |
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BANDWIDTH |
4.0 |
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2.0 |
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GAIN |
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0 |
1.0 |
10 |
100 |
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0.1 |
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COLLECTOR CURRENT (mA) |
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FIGURE 4. NPN GAIN BANDWIDTH PRODUCT vs COLLECTOR CURRENT (UHF 3 x 50 WITH BOND PADS)
Spec Number 511120
6
HFA3127
Ceramic Dual-In-Line Frit Seal Packages (CerDIP)
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c1 |
LEAD FINISH |
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-A- |
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-D- |
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BASE |
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(c) |
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E |
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METAL |
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b1 |
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M |
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M |
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-B- |
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(b) |
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SECTION A-A |
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bbb S |
C |
A - B S |
D S |
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D
BASE |
Q |
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PLANE |
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-C- |
A |
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SEATING |
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PLANE |
L |
α |
S1 |
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eA |
A A |
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b2 |
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b |
e |
eA/2 |
c |
ccc M C A - B S |
D S |
aaa M C A - B S |
D S |
NOTES:
1.Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark.
2.The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.
3.Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.
4.Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.
5.This dimension allows for off-center lid, meniscus, and glass overrun.
6.Dimension Q shall be measured from the seating plane to the base plane.
7.Measure dimension S1 at all four corners.
8.N is the maximum number of terminal positions.
9.Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10.Controlling dimension: INCH.
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
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INCHES |
MILLIMETERS |
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SYMBOL |
MIN |
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MAX |
MIN |
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MAX |
NOTES |
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A |
- |
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0.200 |
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5.08 |
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b |
0.014 |
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0.026 |
0.36 |
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0.66 |
2 |
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b1 |
0.014 |
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0.023 |
0.36 |
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0.58 |
3 |
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b2 |
0.045 |
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0.065 |
1.14 |
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1.65 |
- |
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b3 |
0.023 |
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0.045 |
0.58 |
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1.14 |
4 |
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c |
0.008 |
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0.018 |
0.20 |
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0.46 |
2 |
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c1 |
0.008 |
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0.015 |
0.20 |
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0.38 |
3 |
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D |
- |
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0.840 |
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21.34 |
5 |
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E |
0.220 |
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0.310 |
5.59 |
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7.87 |
5 |
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e |
0.100 BSC |
2.54 BSC |
- |
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eA |
0.300 BSC |
7.62 BSC |
- |
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eA/2 |
0.150 BSC |
3.81 BSC |
- |
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L |
0.125 |
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0.200 |
3.18 |
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5.08 |
- |
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Q |
0.015 |
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0.060 |
0.38 |
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1.52 |
6 |
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S1 |
0.005 |
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0.13 |
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7 |
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α |
90o |
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105o |
90o |
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105o |
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aaa |
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0.015 |
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0.38 |
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bbb |
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0.030 |
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0.76 |
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ccc |
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0.010 |
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0.25 |
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M |
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0.0015 |
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0.038 |
2, 3 |
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N |
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16 |
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16 |
8 |
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Rev. 0 4/94
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
Sales Office Headquarters
For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS
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NORTH ASIA |
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Harris Semiconductor |
Harris Semiconductor |
Harris Semiconductor H.K. Ltd. |
Harris K.K. |
|||
P. O. Box 883, Mail Stop 53-210 |
Mercure Center |
13/F Fourseas Building |
Kojimachi-Nakata Bldg. 4F |
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Melbourne, FL 32902 |
100, Rue de la Fusee |
208-212 Nathan Road |
5-3-5 Kojimachi |
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TEL: 1-800-442-7747 |
1130 Brussels, Belgium |
Tsimshatsui, Kowloon |
Chiyoda-ku, Tokyo 102 Japan |
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(407) 729-4984 |
TEL: (32) 2-724-2111 |
Hong Kong |
TEL: (81) |
3-3265-7571 |
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FAX: (407) 729-5321 |
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TEL: (852) 723-6339 |
TEL: (81) |
3-3265-7572 (Sales) |
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S E M I C O N D U C T O R
Spec Number 511120
7