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HGTD3N60C3, HGTD3N60C3S

Test Circuit and Waveforms

 

 

 

L = 1mH

 

90%

 

 

 

 

RHRD460

 

 

10%

 

 

VGE

 

 

 

RG = 82Ω

 

EOFF

EON

 

VCE

 

 

 

 

+

VDD = 480V

90%

 

 

 

-

 

 

 

10%

 

 

 

 

 

 

ICE

 

 

 

tD(OFF)I

tRI

 

 

tFI

tD(ON)I

 

 

 

FIGURE 18. INDUCTIVE SWITCHING TEST CIRCUIT

FIGURE 19. SWITCHING TEST WAVEFORMS

Handling Precautions for IGBTs

Insulated Gate Bipolar Transistors are susceptible to gateinsulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBT’s are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBT’s can be handled safely if the following basic precautions are taken:

1.Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as “ECCOSORBD LD26” or equivalent.

2.When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband.

3.Tips of soldering irons should be grounded.

4.Devices should never be inserted into or removed from circuits with power on.

5.Gate Voltage Rating - Never exceed the gate-voltage rat-

ing of VGEM. Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region.

6.Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate open-cir- cuited or floating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup.

7.Gate Protection - These devices do not have an internal monolithic zener diode from gate to emitter. If gate protection is required an external zener is recommended.

Trademark Emerson and Cumming, Inc.

Operating Frequency Information

Operating Frequency Information for a Typical Device

Figure 13 is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (ICE) plots are possible using the information shown for a typical unit in Figures 4, 7, 8, 11 and 12. The operating frequency plot (Figure 13) of a typical device

shows fMAX1 or fMAX2 whichever is smaller at each point. The information is based on measurements of a typical

device and is bounded by the maximum rated junction temperature.

fMAX1 is defined by fMAX1 = 0.05/(tD(OFF)I+ tD(ON)I). Deadtime (the denominator) has been arbitrarily held to 10% of

the onstate time for a 50% duty factor. Other definitions are possible. tD(OFF)I and tD(ON)I are defined in Figure 19.

Device turn-off delay can establish an additional frequency limiting condition for an application other than TJMAX.

tD(OFF)I is important when controlling output ripple under a lightly loaded condition.

fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON). The allowable dissipation (PD) is defined by PD = (TJMAX -

TC)/RθJC. The sum of device switching and conduction losses must not exceed PD. A 50% duty factor was used (Figure 13) and the conduction losses (PC) are approximated by PC =

(VCE x ICE)/2. EON and EOFF are defined in the switching waveforms shown in Figure 19. EON is the integral of the

instantaneous power loss (ICE x VCE) during turn-on and EOFF is the integral of the instantaneous power loss (ICE x VCE) during turn-off. All tail losses are included in the calculation for EOFF; i.e. the collector current equals zero (ICE = 0).

6

HGTD3N60C3, HGTD3N60C3S

Packaging

 

E

A

H1

b2

A1

TERM. 4

SEATING

PLANE

D

b1

L1

L

b

 

 

c

1

2

3

 

 

e

 

J1

 

e1

 

 

 

LEAD #

TERMINAL

Lead No. 1

 

Gate

Lead No. 2

 

Collector

Lead No. 3

 

Emitter

Term. 4

 

Collector

Mounting Flange

 

TO-251AA

3 LEAD JEDEC TO-251AA PLASTIC PACKAGE

 

INCHES

MILLIMETERS

 

SYMBOL

 

 

 

 

NOTES

MIN

MAX

MIN

MAX

 

 

 

 

 

 

A

0.086

0.094

2.19

2.38

-

 

 

 

 

 

 

A1

0.018

0.022

0.46

0.55

3, 4

b

0.028

0.032

0.72

0.81

3, 4

 

 

 

 

 

 

b1

0.033

0.040

0.84

1.01

3

b2

0.205

0.215

5.21

5.46

3, 4

c

0.018

0.022

0.46

0.55

3, 4

 

 

 

 

 

 

D

0.270

0.290

6.86

7.36

-

 

 

 

 

 

 

E

0.250

0.265

6.35

6.73

-

 

 

 

 

 

 

e

0.090 TYP

2.28 TYP

5

 

 

 

 

e1

0.180 BSC

4.57 BSC

5

H1

0.035

0.045

0.89

1.14

-

J1

0.040

0.045

1.02

1.14

6

L

0.355

0.375

9.02

9.52

-

 

 

 

 

 

 

L1

0.075

0.090

1.91

2.28

2

NOTES:

1.These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88.

2.Solder finish uncontrolled in this area.

3.Dimension (without solder).

4.Add typically 0.002 inches (0.05mm) for solder plating.

5.Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D.

6.Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D.

7.Controlling dimension: Inch.

8.Revision 2 dated 10-95.

7

HGTD3N60C3, HGTD3N60C3S

Packaging (Continued)

E

A

TO-252AA

H1

b2

A1

SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE

 

INCHES

MILLIMETERS

 

 

 

SEATING

 

 

 

 

SYMBOL

MIN

MAX

MIN

MAX

NOTES

 

 

PLANE

D

 

 

A

0.086

0.094

2.19

2.38

-

 

 

A1

0.018

0.022

0.46

0.55

4, 5

 

 

 

 

L 2

 

b

0.028

0.032

0.72

0.81

4, 5

 

 

L

b1

0.033

0.040

0.84

1.01

4

1

3

b2

0.205

0.215

5.21

5.46

4, 5

 

 

 

 

b

b1

L1

b3

0.190

-

4.83

-

2

 

e

c

0.018

0.022

0.46

0.55

4, 5

 

c

 

e1

J1

D

0.270

0.290

6.86

7.36

-

 

 

0.265

E

0.250

0.265

6.35

6.73

-

TERM. 4

(6.7)

e

0.090 TYP

2.28 TYP

7

 

 

 

 

 

 

e1

0.180 BSC

4.57 BSC

7

 

L3

0.265 (6.7)

H1

0.035

0.045

0.89

1.14

-

b3

J1

0.040

0.045

1.02

1.14

-

 

 

 

 

 

L

0.100

0.115

2.54

2.92

-

 

0.070 (1.8)

 

L1

0.020

-

0.51

-

4, 6

 

 

L2

0.025

0.040

0.64

1.01

3

 

 

 

BACK VIEW

0.118 (3.0)

L3

0.170

-

4.32

-

2

 

NOTES:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.063 (1.6)

0.063 (1.6)

1. These dimensions are within allowable dimensions of Rev. B of

 

JEDEC TO-252AA outline dated 9-88.

 

 

 

0.090 (2.3)

 

 

 

 

 

2. L3 and b3 dimensions establish a minimum mounting surface for

 

 

0.090 (2.3)

 

 

terminal 4.

 

 

 

 

 

 

 

 

 

 

 

 

MINIMUM PAD SIZE RECOMMENDED FOR

3. Solder finish uncontrolled in this area.

 

 

 

SURFACE-MOUNTED APPLICATIONS

4. Dimension (without solder).

 

 

 

 

 

 

 

 

 

 

 

 

5. Add typically 0.002 inches (0.05mm) for solder plating.

 

 

LEAD

TERMINAL

6. L1 is the terminal length for soldering.

 

 

 

7. Position of lead to be measured 0.090 inches (2.28mm) from bottom

 

 

 

 

Lead No. 1

Gate

of dimension D.

 

 

 

 

 

8. Controlling dimension: Inch.

 

 

 

 

 

 

 

 

 

 

Lead No. 3

Emitter

9. Revision 5 dated 10-95.

 

 

 

 

Term. No. 4

Collector

 

 

 

 

 

 

 

Mounting Flange

 

 

 

 

 

 

 

8

HGTD3N60C3, HGTD3N60C3S

Packaging (Continued)

TO-252AA

16mm TAPE AND REEL

22.4mm

1.5mm

4.0mm

 

 

2.0mm

1.75mm

 

DIA. HOLE

13mm

C

 

L

16mm

330mm

 

50mm

 

 

 

 

 

8.0mm

16.4mm

USER DIRECTION OF FEED

GENERAL INFORMATION

COVER TAPE

1. USE "9A" SUFFIX ON PART NUMBER.

 

 

2. 2500 PIECES PER REEL.

 

3. ORDER IN MULTIPLES OF FULL REELS ONLY.

 

4. MEETS EIA-481 REVISION "A" SPECIFICATIONS.

Revision 5 dated 10-95

All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.

Sales Office Headquarters

For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS

NORTH AMERICA

EUROPE

ASIA

Harris Semiconductor

Harris Semiconductor

Harris Semiconductor PTE Ltd.

P. O. Box 883, Mail Stop 53-210

Mercure Center

No. 1 Tannery Road

Melbourne, FL 32902

100, Rue de la Fusee

Cencon 1, #09-01

TEL: 1-800-442-7747

1130 Brussels, Belgium

Singapore 1334

(407) 729-4984

TEL: (32) 2.724.2111

TEL: (65) 748-4200

FAX: (407) 729-5321

FAX: (32) 2.724.22.05

FAX: (65) 748-0400

 

 

 

 

 

 

 

 

 

S E M I C O N D U C T O R

 

9

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