Материал: 4HCT161A
MC54/74HCT161A MC54/74HCT163A |
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T0 |
14 |
Q0 |
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Q0 |
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R |
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C |
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C |
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Load |
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3 |
Load |
Q0 |
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P0 |
P0 |
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T1 |
13 |
Q1 |
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R |
Q1 |
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C |
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C |
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Load |
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4 |
Load |
Q1 |
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P1 |
P1 |
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T2 |
12 |
Q2 |
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R |
Q2 |
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C |
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C |
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Load |
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5 |
Load |
Q2 |
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P2 |
P2 |
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T3 |
11 |
Q3 |
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Q3 |
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R |
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C |
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C |
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Load |
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6 |
Load |
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P3 |
P3 |
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15 |
Ripple |
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Carry Out |
7 |
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Enable P |
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10 |
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Enable T |
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Reset 1
Load 9
2
Clock
R
Load
Load
C
C
The flip±flops shown in the circuit diagrams are Toggle± Enable flip±flops. A Toggle±Enable flip±flop is a combination of a D flip±flop and a T flip±flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip±flop. The logic level at the Pn input is then clocked to the Q output of the flip±flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip±flop low.
Figure 8. 4±Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)
MOTOROLA |
6 |
Reset (HCT161A)
Reset (HCT163A)
Load
P0
Preset P1
Data
Inputs
P2
P3
Clock (HCT161A)
Clock (HCT163A)
Enable P
Count
Enables
Enable T
Q0
Q1
Outputs
Q2
Q3
Ripple Carry Out
MC54/74HCT161A MC54/74HCT163A
(Asynchronous)
(Synchronous)
12 |
13 |
14 |
15 |
0 |
1 |
2 |
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Count |
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Inhibit |
Reset Load
Figure 9. Timing Diagram
7 |
MOTOROLA |
MC54/74HCT161A MC54/74HCT163A |
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T0 |
14 |
Q0 |
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Q0 |
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R |
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C |
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C |
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Load |
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3 |
Load |
Q0 |
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P0 |
P0 |
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T1 |
13 |
Q1 |
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R |
Q1 |
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C |
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C |
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Load |
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4 |
Load |
Q1 |
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P1 |
P1 |
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T2 |
12 |
Q2 |
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R |
Q2 |
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C |
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C |
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Load |
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5 |
Load |
Q2 |
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P2 |
P2 |
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T3 |
11 |
Q3 |
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Q3 |
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R |
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C |
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C |
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Load |
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6 |
Load |
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P3 |
P3 |
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15 |
Ripple |
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Carry Out |
7 |
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Enable P |
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10 |
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Enable T |
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Reset 1
Load 9
2
Clock
R
Load
Load
C
C
The flip±flops shown in the circuit diagrams are Toggle± Enable flip±flops. A Toggle±Enable flip±flop is a combination of a D flip±flop and a T flip±flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip±flop. The logic level at the Pn input is then clocked to the Q output of the flip±flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip±flop low.
Figure 10. 4±Bit Binary Counter with Synchronous Reset (MC54/74HCT163A)
MOTOROLA |
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MC54/74HCT161A MC54/74HCT163A |
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TYPICAL APPLICATIONS CASCADING |
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Load |
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Inputs |
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Inputs |
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Inputs |
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H=Count |
Load Q0Q1 Q2Q3 |
Load |
Q0Q1 Q2Q3 |
Load |
Q0Q1 Q2Q3 |
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Enable P |
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Enable P |
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Enable P |
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L=Disable |
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Ripple |
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Ripple |
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Ripple |
To More |
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H=Count |
Enable T |
Enable T |
Enable T |
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Carry |
Carry |
Carry |
Significant |
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L=Disable |
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Out |
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Out |
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Out |
Stages |
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Clock |
Clock |
Clock |
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Reset Q0Q1 Q2Q3 |
Reset Q0Q1 Q2Q3 |
Reset Q0Q1 Q2Q3 |
Reset |
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Outputs |
Outputs |
Outputs |
Clock |
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NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set±up times between Enable (port) and clock.
Figure 11. N±Bit Synchronous Counters
Inputs |
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Inputs |
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Inputs |
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Load
Enable P
Enable T |
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Load Q0Q1 Q2Q3 |
Load Q0Q1 Q2Q3 |
Load Q0Q1 Q2Q3 |
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Enable P |
Ripple |
Enable P |
Ripple |
Enable P |
Ripple |
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Enable T |
Enable T |
Enable T |
To More |
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Carry |
Carry |
Carry |
Significant |
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Clock |
Clock |
Out |
Clock |
Out |
Clock |
Out |
Stages |
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Reset |
Q0Q1 Q2Q3 |
Reset |
Q0Q1 Q2Q3 |
Reset |
Q0Q1 Q2Q3 |
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Reset |
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Outputs |
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Outputs |
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Outputs |
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Figure 12. Nibble Ripple Counter
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MOTOROLA |
MC54/74HCT161A MC54/74HCT163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HCT163A |
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HCT163A |
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Other |
Q0 |
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Other |
Q0 |
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Inputs |
Q1 |
Optional Buffer |
Inputs |
Q1 |
Optional Buffer |
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for Noise Rejection |
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for Noise Rejection |
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Q2 |
Output |
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Q2 |
Output |
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Q3 |
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Q3 |
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Reset |
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Reset |
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Figure 13. Modulo±5 Counter Figure 14. Modulo±11 Counter
The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitch± free due to the synchronous Reset.
MOTOROLA |
10 |