Материал: sn74ahct1g08
SN74AHCT1G08
SCLS315Q –MARCH 1996 –REVISED APRIL 2016 |
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www.ti.com |
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7 Parameter Measurement Information |
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VCC |
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Ω S1 |
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RL = 1 |
Open |
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TEST |
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S1 |
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From Output |
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Test |
From Output |
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k |
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GND |
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Under Test |
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Point |
Under Test |
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tPLH/tPHL |
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Open |
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CL |
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CL |
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tPLZ/tPZL |
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VCC |
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(see Note A) |
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(see Note A) |
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tPHZ/tPZH |
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GND |
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Open Drain |
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VCC |
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LOAD CIRCUIT FOR |
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LOAD CIRCUIT FOR |
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TOTEM-POLE OUTPUTS |
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3-STATE AND OPEN-DRAIN OUTPUTS |
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3 V |
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Timing Input |
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1.5 V |
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0 V |
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th |
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3 V |
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tsu |
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3 V |
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1.5 V |
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1.5 V |
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Input |
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Data Input |
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1.5 V |
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1.5 V |
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0 V |
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0 V |
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VOLTAGE WAVEFORMS
PULSE DURATION
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3 V |
Input |
1.5 V |
1.5 V |
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0 V |
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tPLH |
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tPHL |
In-Phase |
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VOH |
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50% VCC |
50% VCC |
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Output |
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VOL |
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tPHL |
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tPLH |
Out-of-Phase |
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VOH |
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50% VCC |
50% VCC |
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Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
CL includes probe and jig capacitance.
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output |
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3 V |
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1.5 V |
1.5 V |
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Control |
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0 V |
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tPZL |
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tPLZ |
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Output |
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≈VCC |
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Waveform 1 |
50% VCC |
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S1 at VCC |
VOL + 0.3 V |
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(see Note B) |
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VOL |
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tPZH |
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tPHZ |
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Output |
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VOH |
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Waveform 2 |
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S1 at GND |
50% VCC |
VOH − 0.3 V |
(see Note B) |
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≈0 V |
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VOLTAGE WAVEFORMS |
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ENABLE AND DISABLE TIMES
LOWAND HIGH-LEVEL ENABLING
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
The outputs are measured one at a time with one input transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6 |
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Copyright © 1996–2016, Texas Instruments Incorporated |
Product Folder Links: SN74AHCT1G08
SN74AHCT1G08
www.ti.com |
SCLS315Q –MARCH 1996–REVISED APRIL 2016 |
8 Detailed Description
8.1 Overview
The SN74AHCT1G08 device is a single 2-input positive-AND gate. The device performs the Boolean AND function (Y = A • B or Y = A + B) in positive logic. Low ICC current allows this device to be used in powersensitive or battery-powered applications. Robust inputs allow the device to up-translate with a propagation delay of 20 ns.
8.2 Functional Block Diagram
A |
1 |
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Y |
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2 |
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B |
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Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The VCC for the device is optimized at 5 V.
Up voltage translation from 3.3 V to 5 V is allowed. The inputs accept VIH levels of 2 V. Output ringing is minimized by slow edge rates.
Inputs are TTL-Voltage compatible.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AHCT1G08.
Table 1. Function Table
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OUTPUT |
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Y |
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L |
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X |
L |
X |
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L |
L |
Copyright © 1996–2016, Texas Instruments Incorporated |
Submit Documentation Feedback |
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Product Folder Links: SN74AHCT1G08
SN74AHCT1G08
SCLS315Q –MARCH 1996 –REVISED APRIL 2016 |
www.ti.com |
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHCT1G08 device is a single AND gate, which is often used for many common functions like power sequencing or an on LED indicator. Because the device is configured to output LOW unless all inputs are HIGH, an LED tied to the output of the device will only turn HIGH when all systems connected are sending a HIGH, or ready signal.
9.2 Typical Application
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AND Logic Function |
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Basic LED Driver |
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VCC |
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VCC |
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A– uC or Logic |
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A– uC or Logic |
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Y– uC or Logic |
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B– uC or Logic |
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AHCT1G08 |
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B– uC or Logic |
AHCT1G08 |
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Copyright © 2016, Texas Instruments Incorporated
Figure 4. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see t/ V in Recommended Operating Conditions.
–For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
–Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2.Recommended Output Conditions
–Load currents must not exceed 25 mA per output and 50 mA total for the part.
–Outputs must not be pulled above VCC.
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Copyright © 1996–2016, Texas Instruments Incorporated |
Product Folder Links: SN74AHCT1G08
SN74AHCT1G08
www.ti.com |
SCLS315Q –MARCH 1996–REVISED APRIL 2016 |
Typical Application (continued)
9.2.3 Application Curve
Voltage (V)
5.5 |
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5 |
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AHCT1G08 |
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AC |
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4.5 |
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HC |
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4 |
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VI |
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3.5 |
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3 |
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2.5 |
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2 |
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1.5 |
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1 |
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0.5 |
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0 |
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–0.5 |
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–1.5 |
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0 |
2 |
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Time (ns) |
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VCC = 5 V |
Load = 50 Ω / 50 pF |
Figure 5. Typical Switching Characteristics
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends a 0.1-µF capacitor for devices with a single supply; and a 0.01-µF or 0.022-µF capactor for each power pin if there are multiple VCC pins. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Observe the following rules under all circumstances.
•All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
•The logic level that must be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever make more sense or is more convenient.
11.2 Layout Example
VCC |
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Input |
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Unused Input |
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Output |
Unused Input |
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Output |
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Input |
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Figure 6. |
Layout Diagram |
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Copyright © 1996–2016, Texas Instruments Incorporated |
Submit Documentation Feedback |
9 |
Product Folder Links: SN74AHCT1G08
SN74AHCT1G08
SCLS315Q –MARCH 1996 –REVISED APRIL 2016 |
www.ti.com |
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation.
10 |
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Copyright © 1996–2016, Texas Instruments Incorporated |
Product Folder Links: SN74AHCT1G08